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Repositories in this selection 6 · UTC 2026-11-04
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1—Llogisim-evolution / logisim-evolutionDigital logic design tool and simulatorJavaGPL-3.0 · Share derivative sourceInsufficient rank history7,8811,051——2026-11-03
2—LLeiWang1999 / FPGAHelp everyone get started with FPGA and share excellent articles and projects related to FPGAUnknownUnknown · Restricted / unknownInsufficient rank history5,839805——2022-05-15
3—Oopen-sdr / openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, softwareCAGPL-3.0 · Share derivative sourceInsufficient rank history4,857828——2026-10-22
4—Cchipsalliance / chiselChisel: A Modern Hardware Design LanguageScalaApache-2.0 · PermissiveInsufficient rank history4,826666——2026-11-02
5—Vverilator / verilatorVerilator open-source SystemVerilog simulator and lint systemSystemVerilogNOASSERTION · Restricted / unknownInsufficient rank history4,053965——2026-11-03
6—Cchili-chips-ba / wireguard-fpgaFull-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!SystemVerilogBSD-3-Clause · PermissiveInsufficient rank history1,37838——2026-11-02
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